`timescale 1ns / 1ps

module leds(reset,clk,frame,irdy,trdy,devsel,idsel,ad,cbe,par,stop,inta,led_out);
    input reset;
    input clk;
    input frame;
    input irdy;
    output trdy;
    output devsel;
    input idsel;
    inout [31:0] ad;
    input [3:0] cbe;
    inout par;
    output stop;
    output inta;
    output led_out;

reg [24:0] counter;
reg led;
assign led_out = led;
assign trdy = 1'bZ;
assign devsel = 1'bZ;
assign ad = 32'bZ;
assign par = 1'bZ;
assign stop = 1'bZ;
assign inta = 1'bZ;

always @(posedge clk)
begin
   if (~reset) begin
        led <= 0;
		  counter = 0;
	end
	else
	begin
		counter = counter + 1;
		led <= counter[24];
	end
end
endmodule